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Mostrati risultati da 1 a 20 di 124
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Parameterised System Design Based on Genetic Algorithms 1-gen-2001 Ascia, G; Catania, V.; Palesi, Maurizio
A Novel Approach to Design Space Exploration of Parameterized SOCs 1-gen-2001 Ascia, G; Catania, V.; Palesi, Maurizio
An Instruction-Level Power Analysis Model with Data Dependency 1-gen-2001 Ascia, G.; Catania, V; Palesi, Maurizio; Sarta, D.
Design Space Exploration Methodologies for IP-based System-on-a-chip 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
A Framework for Design Space Exploration of Parameterized VLSI Systems 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
Multi-objective design space exploration using genetic algorithms 1-gen-2002 Palesi, Maurizio; Givargis, T.
Tuning methodologies for parameterized systems design 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
Tuning methodologies for parameterized systems design 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
An evolutionary approach for Pareto-optimal configurations in SOC platforms 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
A genetic bus encoding technique for power optimization of embedded systems 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio
An evolutionary approach for reducing the switching activity in address buses 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
A genetic approach to bus encoding 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
An evolutionary Approach for reducing the energy in address buses 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
Multi-Objective Optimization of a Parameterized VLIW Architecture 1-gen-2004 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Multi-objective mapping for mesh-based NoC architectures 1-gen-2004 Ascia, G; Catania, V.; Palesi, Maurizio
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 1-gen-2004 Ascia, G; Catania, V.; Palesi, Maurizio
An Evolutionary Approach to Network on Chip Mapping Problem 1-gen-2005 Ascia, G; Catania, V.; Palesi, Maurizio
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 1-gen-2005 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 1-gen-2005 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Mostrati risultati da 1 a 20 di 124
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