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Mostrati risultati da 41 a 60 di 124
Titolo Data di pubblicazione Autore(i) File
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 1-gen-2008 Palesi, Maurizio; Longo, G; Signorino, S; Kumar, S; Holsmark, R; Catania, V.
Bandwidth Aware Routing Algorithms for Networks-on-Chip 1-gen-2008 Longo, G; Signorino, S; Palesi, Maurizio; Kumar, S; Holsmark, R; Catania, V.
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 1-gen-2008 Frazzetta, D; Dimartino, G; Palesi, Maurizio; Kumar, S; Catania, V.
High Performance Computing for Embedded System Design: A Case Study 1-gen-2008 Catania, Vincenzo; DE FRANCISCI MORALES, Gianmarco; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
A Communication-Aware Topological Mapping Technique for NoCs 1-gen-2008 Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J.
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip 1-gen-2008 G., Ascia; V., Catania; Palesi, Maurizio; D., Patti
Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions 1-gen-2008 R., Holsmark; Palesi, Maurizio; S., Kumar
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 1-gen-2008 V., Catania; Palesi, Maurizio; D., Patti
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 1-gen-2009 Holsmark, R; Palesi, Maurizio; Kumar, S; Mejia, A.
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 1-gen-2009 Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M.
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 1-gen-2009 Ascia, G; Catania, V; Fazzino, F; Palesi, Maurizio
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 1-gen-2009 Palesi, Maurizio; Fazzino, F; Ascia, G; Catania, V.
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 1-gen-2009 Vincenzo, Catania; GIANMARCO DE FRANCISCI, Morales; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
Message from the Chairs 1-gen-2009 Palesi, Maurizio; Kumar, S.
Application Specific Routing Algorithms for Networks on Chip 1-gen-2009 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, V.
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 1-gen-2009 Palesi, Maurizio; Kumar, S; Catania, V.
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 1-gen-2009 Mejia, A; Palesi, Maurizio; Flich, J; Kumar, S; Lopez, P; Holsmark, R; Duato, J.
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 1-gen-2010 R., Holsmark; S., Kumar; Palesi, Maurizio
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 1-gen-2010 M., Yang; Y., Jiang; P., Liu; Palesi, Maurizio
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 1-gen-2010 Palesi, Maurizio; Holsmark, R; Wang, X; Kumar, S; Yang, M; Jiang, Y; Catania, V.
Mostrati risultati da 41 a 60 di 124
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