Sfoglia per Autore
Exploring Design Space of VLIW Architectures
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Mapping Cores on Network-on-Chip
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Power/Energy Perspective on Hyperblock Formation
2005-01-01 Ascia, G; Catania, V; Palesi, Maurizio; Patti, D.
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design
2006-01-01 Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures
2006-01-01 Palesi, Maurizio; Kumar, S; Holsmark, R.
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
2006-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
2006-01-01 Holsmark, R; Palesi, Maurizio; Kumar, S.
Improving Wormhole Adaptive Routing in Networks on Chip
2006-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Fuzzy Decision Making in Embedded System Design
2006-01-01 DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti; Giuseppe, Ascia; Vincenzo, Catania
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems
2006-01-01 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, V.
A new selection policy for adaptive routing in network on chip
2006-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design
2006-01-01 Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
2006-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems
2007-01-01 DI NUOVO, Alessandro; Palesi, Maurizio; Vincenzo, Catania
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms
2007-01-01 Palesi, Maurizio; Kumar, S; Holsmark, R; Catania, V.
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip
2007-01-01 Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
Networks-on-Chip: Emerging Research Topics and Novel Ideas
2007-01-01 Bertozzi, D; Kumar, S; Palesi, Maurizio
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario
2007-01-01 Catania, V; Palesi, Maurizio; Patti, D.
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