PALESI, MAURIZIO

PALESI, MAURIZIO  

Facoltà di Ingegneria e Architettura  

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2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 1-gen-2015 Catania, Vincenzo; Mineo, Andrea; Monteleone, Salvatore; Palesi, Maurizio; Patti, Davide .
A Communication-Aware Topological Mapping Technique for NoCs 1-gen-2008 Tornero, R; ORDUNA J., M; Palesi, Maurizio; Duato, J.
A Framework for Design Space Exploration of Parameterized VLSI Systems 1-gen-2002 Ascia, G; Catania, V.; Palesi, Maurizio
A genetic approach to bus encoding 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
A genetic bus encoding technique for power optimization of embedded systems 1-gen-2003 Ascia, G; Catania, V.; Palesi, Maurizio
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 1-gen-2006 Palesi, Maurizio; Kumar, S; Holsmark, R.
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 1-gen-2006 Palesi, Maurizio; Holsmark, R; Kumar, S; Catania, V.
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 1-gen-2010 R., Holsmark; S., Kumar; Palesi, Maurizio
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 1-gen-2009 Tornero, R; Sterrantino, V; Palesi, Maurizio; Orduna, J. M.
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 1-gen-2006 Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
A new selection policy for adaptive routing in network on chip 1-gen-2006 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
A Novel Approach to Design Space Exploration of Parameterized SOCs 1-gen-2001 Ascia, G; Catania, V.; Palesi, Maurizio
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 1-gen-2005 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 1-gen-2014 X. Wang, X.; Zhao, B.; Mak, T.; Yang, M.; Jiang, Y.; Daneshtalab, M.; Palesi, Maurizio
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 1-gen-2013 Ascia, G.; Palesi, Maurizio; Catania, V.
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 1-gen-2010 Palesi, Maurizio; Holsmark, R; Wang, X; Kumar, S; Yang, M; Jiang, Y; Catania, V.
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 1-gen-2014 Mineo, A.; Palesi, Maurizio; Ascia, G.; Catania, V.
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 1-gen-2009 Vincenzo, Catania; GIANMARCO DE FRANCISCI, Morales; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 1-gen-2006 Giuseppe, Ascia; Vincenzo, Catania; DI NUOVO, Alessandro; Palesi, Maurizio; Davide, Patti
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 1-gen-2009 Ascia, G; Catania, V; Fazzino, F; Palesi, Maurizio