Sfoglia per Autore PALESI, MAURIZIO
Parameterised System Design Based on Genetic Algorithms
2001-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
A Novel Approach to Design Space Exploration of Parameterized SOCs
2001-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
An Instruction-Level Power Analysis Model with Data Dependency
2001-01-01 Ascia, G.; Catania, V; Palesi, Maurizio; Sarta, D.
Design Space Exploration Methodologies for IP-based System-on-a-chip
2002-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Multi-objective design space exploration using genetic algorithms
2002-01-01 Palesi, Maurizio; Givargis, T.
A Framework for Design Space Exploration of Parameterized VLSI Systems
2002-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Tuning methodologies for parameterized systems design
2002-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Tuning methodologies for parameterized systems design
2002-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
An evolutionary approach for Pareto-optimal configurations in SOC platforms
2002-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
A genetic bus encoding technique for power optimization of embedded systems
2003-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
An evolutionary approach for reducing the switching activity in address buses
2003-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
A genetic approach to bus encoding
2003-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
An evolutionary Approach for reducing the energy in address buses
2003-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Parlato, A.
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration
2003-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Multi-objective mapping for mesh-based NoC architectures
2004-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
Multi-Objective Optimization of a Parameterized VLIW Architecture
2004-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms
2004-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio; Patti, D.
An Evolutionary Approach to Network on Chip Mapping Problem
2005-01-01 Ascia, G; Catania, V.; Palesi, Maurizio
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