IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 5.243
EU - Europa 4.099
AS - Asia 1.646
SA - Sud America 378
Continente sconosciuto - Info sul continente non disponibili 18
AF - Africa 17
Totale 11.401
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Nazione #
US - Stati Uniti d'America 5.003
IE - Irlanda 1.479
SG - Singapore 841
UA - Ucraina 782
FR - Francia 615
GB - Regno Unito 465
BR - Brasile 337
HK - Hong Kong 309
DE - Germania 240
CN - Cina 233
CA - Canada 214
SE - Svezia 165
CH - Svizzera 130
FI - Finlandia 98
IN - India 70
TR - Turchia 53
VN - Vietnam 40
RU - Federazione Russa 25
IR - Iran 23
IT - Italia 22
EU - Europa 17
KR - Corea 17
MX - Messico 16
AR - Argentina 15
PL - Polonia 14
CZ - Repubblica Ceca 11
IQ - Iraq 11
NL - Olanda 9
BE - Belgio 8
ES - Italia 8
JP - Giappone 8
DK - Danimarca 6
EC - Ecuador 6
PE - Perù 6
UZ - Uzbekistan 6
ZA - Sudafrica 6
BD - Bangladesh 5
IL - Israele 5
PY - Paraguay 5
PK - Pakistan 4
AL - Albania 3
CL - Cile 3
HU - Ungheria 3
LT - Lituania 3
MA - Marocco 3
SA - Arabia Saudita 3
AM - Armenia 2
AZ - Azerbaigian 2
BN - Brunei Darussalam 2
DZ - Algeria 2
HN - Honduras 2
JM - Giamaica 2
KG - Kirghizistan 2
OM - Oman 2
RO - Romania 2
TN - Tunisia 2
VE - Venezuela 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BO - Bolivia 1
CO - Colombia 1
DO - Repubblica Dominicana 1
EE - Estonia 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
GT - Guatemala 1
GY - Guiana 1
ID - Indonesia 1
IM - Isola di Man 1
IS - Islanda 1
JO - Giordania 1
KZ - Kazakistan 1
LB - Libano 1
LV - Lettonia 1
NG - Nigeria 1
NI - Nicaragua 1
NP - Nepal 1
PR - Porto Rico 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TT - Trinidad e Tobago 1
TW - Taiwan 1
UG - Uganda 1
UY - Uruguay 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 11.401
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Città #
Dublin 1.475
Chandler 905
Dallas 847
Jacksonville 773
London 418
Singapore 383
Hong Kong 308
Boardman 274
Toronto 193
Ashburn 190
Beijing 150
San Jose 144
Santa Clara 136
Zurich 130
The Dalles 128
Princeton 124
Wilmington 121
Helsinki 97
Chicago 73
Dearborn 59
Istanbul 38
Cedar Knolls 35
São Paulo 28
Frankfurt am Main 22
Norwalk 22
Des Moines 21
Los Angeles 19
Seoul 17
Leawood 16
Pune 15
Edinburgh 14
Cambridge 13
San Francisco 13
Kocaeli 12
Augusta 11
Brno 11
Hanoi 11
New York 11
Rio de Janeiro 11
Bremen 10
Munich 10
Ardabil 9
Ho Chi Minh City 9
Kunming 9
San Mateo 9
Belo Horizonte 8
Brooklyn 8
Brussels 8
Milan 8
Monmouth Junction 8
Ottawa 8
Tokyo 8
Zanjan 8
Atlanta 7
Düsseldorf 7
Las Vegas 7
Phoenix 7
Warsaw 7
Amsterdam 6
Copenhagen 6
Fairfield 6
Guarulhos 6
Guwahati 6
Lauterbourg 6
Manchester 6
Moscow 6
Nanjing 6
Redmond 6
Tashkent 6
Bexley 5
Fresnillo 5
Guangzhou 5
Hefei 5
Montreal 5
Porto Alegre 5
Wroclaw 5
Ann Arbor 4
Belém 4
Campinas 4
Chennai 4
Cotia 4
Falkenstein 4
Franca 4
Glasgow 4
Lima 4
Newark 4
Osasco 4
Saint Petersburg 4
Andover 3
Asunción 3
Bangalore 3
Brasília 3
Budapest 3
Contagem 3
Curitiba 3
Dalsjoefors 3
Fortaleza 3
Haiphong 3
Juiz de Fora 3
Maringá 3
Totale 7.608
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Nome #
A genetic bus encoding technique for power optimization of embedded systems 172
A genetic approach to bus encoding 171
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 170
A Framework for Design Space Exploration of Parameterized VLSI Systems 163
A Communication-Aware Topological Mapping Technique for NoCs 163
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 162
Special Section on ESTIMedia’13 159
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 148
Introduction to the special section on on-chip and off-chip network architectures 146
Editorial 144
Exploiting Data Resilience in Wireless Network-on-chip Architectures 144
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 142
Introduction to the special section on ESTIMedia'12 138
Cycle-Accurate Network on Chip Simulation with Noxim 137
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 134
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 128
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 125
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 124
A new selection policy for adaptive routing in network on chip 120
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 117
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 115
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 110
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 109
An evolutionary approach for reducing the switching activity in address buses 108
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 106
Multi-Objective Optimization of a Parameterized VLIW Architecture 105
Bandwidth Aware Routing Algorithms for Networks-on-Chip 105
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 105
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 104
Improving Wormhole Adaptive Routing in Networks on Chip 103
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 102
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 102
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 101
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 100
Power-Aware Selection Policy for Networks on Chip 99
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 99
A Novel Approach to Design Space Exploration of Parameterized SOCs 99
An Evolutionary Approach to Network on Chip Mapping Problem 98
Network-on-chip architectures and design methodologies 98
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 98
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 97
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 96
Tuning methodologies for parameterized systems design 96
Networks-on-Chip: Emerging Research Topics and Novel Ideas 95
An evolutionary Approach for reducing the energy in address buses 94
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 93
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 91
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 91
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 90
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 90
Design Space Exploration Methodologies for IP-based System-on-a-chip 89
High Performance Computing for Embedded System Design: A Case Study 89
Parameterised System Design Based on Genetic Algorithms 88
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 88
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 87
Multi-objective design space exploration using genetic algorithms 86
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 86
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 86
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 86
An evolutionary approach for Pareto-optimal configurations in SOC platforms 86
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 85
Multi-objective mapping for mesh-based NoC architectures 85
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 84
Application Specific Routing Algorithms for Low Power Network on Chip Design 84
Fuzzy Decision Making in Embedded System Design 84
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 83
Many-core System-on-Chip: architectures and applications 83
Message from the Chairs 82
Exploring Design Space of VLIW Architectures 81
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 81
Introduction to the special issue on “Emerging research in Internet of Things” 81
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 79
A Closed Loop Control based Power Manager for WiNoC Architectures 79
An Instruction-Level Power Analysis Model with Data Dependency 79
Data Encoding Schemes in Networks on Chip 78
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 77
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 77
Noxim: An open, extensible and cycle-accurate network on chip simulator 76
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 76
NoC Links Energy Reduction through Link Voltage Scaling 75
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 74
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 74
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 74
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip 74
Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support 74
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints 74
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 74
Editorial of the Special issue on Many-core Embedded Systems 74
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 74
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 73
Tuning methodologies for parameterized systems design 73
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 73
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems 73
Introduction to the special issue on NoC-based many-core architectures 73
An Offline Method for Designing Adaptive Routing Based on Pressure Model 73
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 72
Power/Energy Perspective on Hyperblock Formation 72
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 72
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems 72
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 72
Totale 9.850
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Categoria #
all - tutte 73.397
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 73.397
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021527 0 0 0 0 0 0 1 179 1 139 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.637 46 63 147 19 177 141 107 161 202 216 246 112
2025/20261.950 240 777 265 144 116 191 217 0 0 0 0 0
Totale 11.475