IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 4.958
EU - Europa 4.093
AS - Asia 1.421
SA - Sud America 366
Continente sconosciuto - Info sul continente non disponibili 18
AF - Africa 16
Totale 10.872
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Nazione #
US - Stati Uniti d'America 4.721
IE - Irlanda 1.479
UA - Ucraina 782
SG - Singapore 686
FR - Francia 614
GB - Regno Unito 465
BR - Brasile 332
HK - Hong Kong 305
DE - Germania 239
CA - Canada 214
CN - Cina 193
SE - Svezia 165
CH - Svizzera 130
FI - Finlandia 98
IN - India 67
TR - Turchia 53
IR - Iran 23
RU - Federazione Russa 22
IT - Italia 21
VN - Vietnam 19
EU - Europa 17
KR - Corea 17
MX - Messico 14
PL - Polonia 14
CZ - Repubblica Ceca 11
IQ - Iraq 11
AR - Argentina 9
NL - Olanda 9
BE - Belgio 8
ES - Italia 8
JP - Giappone 7
DK - Danimarca 6
EC - Ecuador 6
PE - Perù 6
ZA - Sudafrica 6
BD - Bangladesh 5
IL - Israele 5
PY - Paraguay 5
UZ - Uzbekistan 5
PK - Pakistan 4
AL - Albania 3
CL - Cile 3
HU - Ungheria 3
LT - Lituania 3
MA - Marocco 3
SA - Arabia Saudita 3
AM - Armenia 2
AZ - Azerbaigian 2
BN - Brunei Darussalam 2
HN - Honduras 2
KG - Kirghizistan 2
OM - Oman 2
RO - Romania 2
TN - Tunisia 2
VE - Venezuela 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BO - Bolivia 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
EE - Estonia 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
GT - Guatemala 1
GY - Guiana 1
ID - Indonesia 1
IM - Isola di Man 1
IS - Islanda 1
JM - Giamaica 1
JO - Giordania 1
KZ - Kazakistan 1
LB - Libano 1
LV - Lettonia 1
NG - Nigeria 1
NI - Nicaragua 1
NP - Nepal 1
PR - Porto Rico 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TT - Trinidad e Tobago 1
TW - Taiwan 1
UG - Uganda 1
UY - Uruguay 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 10.872
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Città #
Dublin 1.475
Chandler 905
Dallas 847
Jacksonville 773
London 418
Singapore 340
Hong Kong 305
Boardman 274
Toronto 193
Beijing 142
Santa Clara 133
Zurich 130
Princeton 124
Wilmington 121
Ashburn 98
Helsinki 97
The Dalles 92
Chicago 73
Dearborn 59
Istanbul 38
Cedar Knolls 35
São Paulo 28
Frankfurt am Main 22
Norwalk 22
Los Angeles 19
Des Moines 18
Seoul 17
Leawood 16
Pune 15
Edinburgh 14
Cambridge 13
San Francisco 13
Kocaeli 12
Augusta 11
Brno 11
New York 11
Bremen 10
Munich 10
Rio de Janeiro 10
Ardabil 9
Kunming 9
San Mateo 9
Belo Horizonte 8
Brooklyn 8
Brussels 8
Milan 8
Monmouth Junction 8
Ottawa 8
Zanjan 8
Atlanta 7
Düsseldorf 7
Las Vegas 7
Phoenix 7
Tokyo 7
Warsaw 7
Amsterdam 6
Copenhagen 6
Fairfield 6
Guarulhos 6
Guwahati 6
Lauterbourg 6
Manchester 6
Nanjing 6
Redmond 6
Bexley 5
Fresnillo 5
Guangzhou 5
Hanoi 5
Hefei 5
Ho Chi Minh City 5
Montreal 5
Porto Alegre 5
Tashkent 5
Wroclaw 5
Ann Arbor 4
Belém 4
Campinas 4
Chennai 4
Cotia 4
Falkenstein 4
Franca 4
Glasgow 4
Lima 4
Newark 4
Osasco 4
Saint Petersburg 4
Andover 3
Asunción 3
Bangalore 3
Brasília 3
Budapest 3
Contagem 3
Curitiba 3
Dalsjoefors 3
Fortaleza 3
Juiz de Fora 3
Maringá 3
Marília 3
Moscow 3
Nanchang 3
Totale 7.263
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Nome #
A genetic approach to bus encoding 165
A genetic bus encoding technique for power optimization of embedded systems 165
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 165
A Framework for Design Space Exploration of Parameterized VLSI Systems 158
A Communication-Aware Topological Mapping Technique for NoCs 158
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 154
Special Section on ESTIMedia’13 154
Introduction to the special section on on-chip and off-chip network architectures 144
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 143
Editorial 143
Exploiting Data Resilience in Wireless Network-on-chip Architectures 140
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 139
Introduction to the special section on ESTIMedia'12 137
Cycle-Accurate Network on Chip Simulation with Noxim 132
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 131
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 120
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 119
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 117
A new selection policy for adaptive routing in network on chip 115
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 112
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 109
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 105
Improving Wormhole Adaptive Routing in Networks on Chip 103
Bandwidth Aware Routing Algorithms for Networks-on-Chip 103
Power-Aware Selection Policy for Networks on Chip 99
Multi-Objective Optimization of a Parameterized VLIW Architecture 99
An evolutionary approach for reducing the switching activity in address buses 98
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 98
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 98
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 98
Network-on-chip architectures and design methodologies 96
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 96
An Evolutionary Approach to Network on Chip Mapping Problem 95
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 95
A Novel Approach to Design Space Exploration of Parameterized SOCs 95
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 94
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 94
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 92
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 92
Networks-on-Chip: Emerging Research Topics and Novel Ideas 92
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 92
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 91
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 91
Tuning methodologies for parameterized systems design 89
An evolutionary Approach for reducing the energy in address buses 89
Design Space Exploration Methodologies for IP-based System-on-a-chip 88
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 88
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 86
Parameterised System Design Based on Genetic Algorithms 86
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 85
High Performance Computing for Embedded System Design: A Case Study 85
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 85
Multi-objective design space exploration using genetic algorithms 84
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 83
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 83
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 82
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 82
Many-core System-on-Chip: architectures and applications 82
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 81
An evolutionary approach for Pareto-optimal configurations in SOC platforms 81
Fuzzy Decision Making in Embedded System Design 81
Message from the Chairs 80
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 80
Application Specific Routing Algorithms for Low Power Network on Chip Design 80
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 79
Multi-objective mapping for mesh-based NoC architectures 79
Exploring Design Space of VLIW Architectures 78
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 78
Introduction to the special issue on “Emerging research in Internet of Things” 78
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 77
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 76
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 76
Data Encoding Schemes in Networks on Chip 76
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 75
An Instruction-Level Power Analysis Model with Data Dependency 75
NoC Links Energy Reduction through Link Voltage Scaling 74
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 73
Noxim: An open, extensible and cycle-accurate network on chip simulator 73
A Closed Loop Control based Power Manager for WiNoC Architectures 73
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 72
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 72
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 71
Tuning methodologies for parameterized systems design 71
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 71
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip 71
Introduction to the special issue on NoC-based many-core architectures 71
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 70
Power/Energy Perspective on Hyperblock Formation 70
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 70
Editorial of the Special issue on Many-core Embedded Systems 70
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems 70
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 70
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 69
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 69
Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support 69
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 69
Introduction to the Special Issue on Network-on-Chip Architectures 69
An Offline Method for Designing Adaptive Routing Based on Pressure Model 69
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 68
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 68
Totale 9.405
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Categoria #
all - tutte 71.068
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 71.068
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021784 0 0 0 124 6 127 1 179 1 139 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.637 46 63 147 19 177 141 107 161 202 216 246 112
2025/20261.421 240 777 265 139 0 0 0 0 0 0 0 0
Totale 10.946