IRIS
PALESI, MAURIZIO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 6.045
EU - Europa 4.182
AS - Asia 1.867
SA - Sud America 411
Continente sconosciuto - Info sul continente non disponibili 92
AF - Africa 26
Totale 12.623
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 5.781
IE - Irlanda 1.480
SG - Singapore 942
UA - Ucraina 787
FR - Francia 627
GB - Regno Unito 469
BR - Brasile 351
HK - Hong Kong 320
CN - Cina 264
DE - Germania 260
CA - Canada 221
SE - Svezia 165
CH - Svizzera 130
FI - Finlandia 98
IN - India 77
TR - Turchia 55
VN - Vietnam 53
IT - Italia 41
RU - Federazione Russa 29
IR - Iran 23
AR - Argentina 19
IQ - Iraq 19
MX - Messico 19
BD - Bangladesh 18
EU - Europa 17
KR - Corea 17
PL - Polonia 17
JP - Giappone 16
ES - Italia 12
NL - Olanda 12
CZ - Repubblica Ceca 11
PK - Pakistan 10
BE - Belgio 9
EC - Ecuador 8
CL - Cile 7
PE - Perù 7
SA - Arabia Saudita 7
DK - Danimarca 6
IL - Israele 6
MA - Marocco 6
UZ - Uzbekistan 6
ZA - Sudafrica 6
CO - Colombia 5
LT - Lituania 5
PY - Paraguay 5
VE - Venezuela 5
HN - Honduras 4
HU - Ungheria 4
ID - Indonesia 4
PH - Filippine 4
AL - Albania 3
AZ - Azerbaigian 3
JM - Giamaica 3
NI - Nicaragua 3
RS - Serbia 3
AM - Armenia 2
BN - Brunei Darussalam 2
CR - Costa Rica 2
DZ - Algeria 2
EG - Egitto 2
GT - Guatemala 2
JO - Giordania 2
KE - Kenya 2
KG - Kirghizistan 2
MY - Malesia 2
NP - Nepal 2
OM - Oman 2
PR - Porto Rico 2
PT - Portogallo 2
RO - Romania 2
TN - Tunisia 2
TT - Trinidad e Tobago 2
TW - Taiwan 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BJ - Benin 1
BO - Bolivia 1
DO - Repubblica Dominicana 1
EE - Estonia 1
GE - Georgia 1
GR - Grecia 1
GY - Guiana 1
HR - Croazia 1
HT - Haiti 1
IM - Isola di Man 1
IS - Islanda 1
KY - Cayman, isole 1
KZ - Kazakistan 1
LB - Libano 1
LK - Sri Lanka 1
LR - Liberia 1
LV - Lettonia 1
MU - Mauritius 1
NG - Nigeria 1
PS - Palestinian Territory 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
SR - Suriname 1
Totale 12.542
Salva come PNG Salva come JPEG
Città #
Dublin 1.476
Chandler 905
Dallas 851
Jacksonville 773
Singapore 475
London 420
San Jose 338
Hong Kong 319
Ashburn 290
Boardman 274
Chicago 210
Toronto 193
The Dalles 163
Beijing 155
Santa Clara 152
Zurich 130
Princeton 124
Wilmington 122
Helsinki 97
Dearborn 59
Frankfurt am Main 41
Istanbul 38
Cedar Knolls 35
São Paulo 29
Des Moines 23
Norwalk 22
Los Angeles 20
New York 17
Seoul 17
Leawood 16
Tokyo 16
Hanoi 15
Phoenix 15
Pune 15
San Francisco 15
Edinburgh 14
Cambridge 13
Council Bluffs 13
Ho Chi Minh City 13
Rio de Janeiro 13
Kocaeli 12
Augusta 11
Brno 11
Bremen 10
Munich 10
Amsterdam 9
Ardabil 9
Belo Horizonte 9
Kunming 9
San Mateo 9
Brooklyn 8
Brussels 8
Milan 8
Monmouth Junction 8
Ottawa 8
Warsaw 8
Zanjan 8
Atlanta 7
Düsseldorf 7
Las Vegas 7
Manchester 7
Wroclaw 7
Copenhagen 6
Fairfield 6
Guangzhou 6
Guarulhos 6
Guwahati 6
Lauterbourg 6
Moscow 6
Nanjing 6
Newark 6
Redmond 6
Tashkent 6
Baghdad 5
Bexley 5
Fresnillo 5
Hefei 5
Hillsboro 5
Karachi 5
Lima 5
Montreal 5
Porto Alegre 5
Ann Arbor 4
Belém 4
Campinas 4
Charlotte 4
Chennai 4
Cotia 4
Curitiba 4
Falkenstein 4
Franca 4
Glasgow 4
Haiphong 4
Jeddah 4
Mexico City 4
Osasco 4
Philadelphia 4
Rome 4
Saint Petersburg 4
Seattle 4
Totale 8.299
Salva come PNG Salva come JPEG
Nome #
A genetic bus encoding technique for power optimization of embedded systems 190
A genetic approach to bus encoding 183
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 183
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 179
A Communication-Aware Topological Mapping Technique for NoCs 178
A Framework for Design Space Exploration of Parameterized VLSI Systems 175
Special Section on ESTIMedia’13 167
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 163
Introduction to the special section on on-chip and off-chip network architectures 159
Exploiting Data Resilience in Wireless Network-on-chip Architectures 158
Editorial 154
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 153
Introduction to the special section on ESTIMedia'12 148
Cycle-Accurate Network on Chip Simulation with Noxim 146
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 141
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 140
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 140
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 134
A new selection policy for adaptive routing in network on chip 126
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 123
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 122
Bandwidth Aware Routing Algorithms for Networks-on-Chip 121
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 119
An evolutionary approach for reducing the switching activity in address buses 117
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 117
Multi-Objective Optimization of a Parameterized VLIW Architecture 116
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 115
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 114
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 114
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 113
Improving Wormhole Adaptive Routing in Networks on Chip 111
Network-on-chip architectures and design methodologies 110
Tuning methodologies for parameterized systems design 110
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 109
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 109
An evolutionary Approach for reducing the energy in address buses 108
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 108
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 108
An Evolutionary Approach to Network on Chip Mapping Problem 107
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 107
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 106
A Novel Approach to Design Space Exploration of Parameterized SOCs 105
Power-Aware Selection Policy for Networks on Chip 104
Networks-on-Chip: Emerging Research Topics and Novel Ideas 104
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 102
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 102
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 101
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 101
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 101
High Performance Computing for Embedded System Design: A Case Study 101
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 100
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 99
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 97
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 97
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 96
Design Space Exploration Methodologies for IP-based System-on-a-chip 96
Parameterised System Design Based on Genetic Algorithms 96
Multi-objective mapping for mesh-based NoC architectures 96
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 95
An evolutionary approach for Pareto-optimal configurations in SOC platforms 95
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 94
Exploring Design Space of VLIW Architectures 93
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 93
Multi-objective design space exploration using genetic algorithms 92
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 92
Noxim: An open, extensible and cycle-accurate network on chip simulator 92
Many-core System-on-Chip: architectures and applications 92
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 91
Fuzzy Decision Making in Embedded System Design 91
An Instruction-Level Power Analysis Model with Data Dependency 90
Application Specific Routing Algorithms for Low Power Network on Chip Design 89
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints 89
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 89
Introduction to the special issue on “Emerging research in Internet of Things” 89
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 87
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 87
Message from the Chairs 86
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 85
Power/Energy Perspective on Hyperblock Formation 85
NoC Links Energy Reduction through Link Voltage Scaling 85
Data Encoding Schemes in Networks on Chip 85
A Closed Loop Control based Power Manager for WiNoC Architectures 85
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 84
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 84
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 84
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 83
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 83
Editorial of the Special issue on Many-core Embedded Systems 83
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 82
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 82
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip 82
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 82
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 82
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 81
Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support 81
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 81
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms 80
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems 80
Introduction to the special issue on NoC-based many-core architectures 80
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip 79
Totale 10.823
Salva come PNG Salva come JPEG
Categoria #
all - tutte 80.749
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 80.749
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022811 0 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.637 46 63 147 19 177 141 107 161 202 216 246 112
2025/20262.960 240 777 265 144 116 191 321 303 297 199 44 63
2026/2027138 49 89 0 0 0 0 0 0 0 0 0 0
Totale 12.623