IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
EU - Europa 3.973
NA - Nord America 3.818
AS - Asia 947
SA - Sud America 127
Continente sconosciuto - Info sul continente non disponibili 18
AF - Africa 5
Totale 8.888
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Nazione #
US - Stati Uniti d'America 3.606
IE - Irlanda 1.479
UA - Ucraina 780
FR - Francia 581
GB - Regno Unito 438
SG - Singapore 358
HK - Hong Kong 269
DE - Germania 210
CA - Canada 204
CN - Cina 193
SE - Svezia 163
CH - Svizzera 130
BR - Brasile 113
FI - Finlandia 98
IN - India 46
IR - Iran 23
IT - Italia 21
EU - Europa 17
KR - Corea 17
RU - Federazione Russa 17
TR - Turchia 13
CZ - Repubblica Ceca 11
BE - Belgio 8
NL - Olanda 8
MX - Messico 7
DK - Danimarca 6
IL - Israele 5
AR - Argentina 4
PL - Polonia 4
ES - Italia 3
HU - Ungheria 3
UZ - Uzbekistan 3
AL - Albania 2
AM - Armenia 2
AZ - Azerbaigian 2
BD - Bangladesh 2
BN - Brunei Darussalam 2
EC - Ecuador 2
JP - Giappone 2
KG - Kirghizistan 2
MA - Marocco 2
PE - Perù 2
PY - Paraguay 2
RO - Romania 2
BA - Bosnia-Erzegovina 1
BG - Bulgaria 1
CL - Cile 1
EE - Estonia 1
EG - Egitto 1
GE - Georgia 1
GY - Guiana 1
ID - Indonesia 1
IM - Isola di Man 1
IQ - Iraq 1
IS - Islanda 1
KZ - Kazakistan 1
LV - Lettonia 1
NP - Nepal 1
PK - Pakistan 1
PR - Porto Rico 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SK - Slovacchia (Repubblica Slovacca) 1
TN - Tunisia 1
UY - Uruguay 1
VE - Venezuela 1
VN - Vietnam 1
XK - ???statistics.table.value.countryCode.XK??? 1
ZA - Sudafrica 1
Totale 8.888
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Città #
Dublin 1.475
Chandler 905
Jacksonville 773
London 412
Boardman 274
Hong Kong 269
Toronto 193
Beijing 142
Singapore 133
Zurich 130
Santa Clara 127
Princeton 124
Wilmington 120
Helsinki 97
Ashburn 84
Chicago 67
Dearborn 59
Cedar Knolls 35
Norwalk 22
Des Moines 17
Seoul 17
Leawood 16
Pune 15
Edinburgh 14
Cambridge 13
Kocaeli 12
Brno 11
Augusta 10
Bremen 10
Los Angeles 10
Ardabil 9
Kunming 9
San Mateo 9
Brussels 8
Milan 8
Monmouth Junction 8
São Paulo 8
Zanjan 8
Ottawa 7
Amsterdam 6
Copenhagen 6
Fairfield 6
Las Vegas 6
Munich 6
Nanjing 6
Redmond 6
Frankfurt am Main 5
Fresnillo 5
Guangzhou 5
Hefei 5
Ann Arbor 4
Belo Horizonte 4
Falkenstein 4
Saint Petersburg 4
Andover 3
Bangalore 3
Belém 3
Budapest 3
Dalsjoefors 3
Glasgow 3
Juiz de Fora 3
Moscow 3
Nanchang 3
Newark 3
Sacramento 3
Seattle 3
Tashkent 3
Tel Aviv 3
Warsaw 3
Aci Catena 2
Asunción 2
Atlanta 2
Azor 2
Baku 2
Bandar Seri Begawan 2
Bishkek 2
Borås 2
Clifton 2
Colombo 2
Formosa 2
Goiânia 2
Guarulhos 2
Hebei 2
Henderson 2
Jaipur 2
Jinan 2
Joinville 2
Jundiaí 2
Madrid 2
Manchester 2
New York 2
Ningbo 2
Paracatu 2
Piracicaba 2
Quito 2
Rabat 2
San Francisco 2
São Bernardo do Campo 2
São José dos Campos 2
Tirana 2
Totale 5.845
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Nome #
A genetic bus encoding technique for power optimization of embedded systems 142
A genetic approach to bus encoding 140
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 140
A Framework for Design Space Exploration of Parameterized VLSI Systems 139
Special Section on ESTIMedia’13 138
A Communication-Aware Topological Mapping Technique for NoCs 136
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 132
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 129
Introduction to the special section on on-chip and off-chip network architectures 129
Introduction to the special section on ESTIMedia'12 126
Editorial 123
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 122
Exploiting Data Resilience in Wireless Network-on-chip Architectures 119
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 116
Cycle-Accurate Network on Chip Simulation with Noxim 113
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 98
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 94
A new selection policy for adaptive routing in network on chip 93
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 91
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 87
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 87
Power-Aware Selection Policy for Networks on Chip 86
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 85
Bandwidth Aware Routing Algorithms for Networks-on-Chip 85
An evolutionary approach for reducing the switching activity in address buses 85
Multi-Objective Optimization of a Parameterized VLIW Architecture 84
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 82
Improving Wormhole Adaptive Routing in Networks on Chip 82
Network-on-chip architectures and design methodologies 81
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 80
An Evolutionary Approach to Network on Chip Mapping Problem 79
Networks-on-Chip: Emerging Research Topics and Novel Ideas 78
Design Space Exploration Methodologies for IP-based System-on-a-chip 76
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 75
Parameterised System Design Based on Genetic Algorithms 75
An evolutionary Approach for reducing the energy in address buses 75
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 75
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 75
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 74
Multi-objective design space exploration using genetic algorithms 73
Tuning methodologies for parameterized systems design 73
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 73
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 72
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 72
A Novel Approach to Design Space Exploration of Parameterized SOCs 72
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 71
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 70
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 70
Fuzzy Decision Making in Embedded System Design 70
Message from the Chairs 69
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 69
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 69
High Performance Computing for Embedded System Design: A Case Study 69
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 68
Multi-objective mapping for mesh-based NoC architectures 68
Exploring Design Space of VLIW Architectures 67
An evolutionary approach for Pareto-optimal configurations in SOC platforms 67
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 67
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 67
Introduction to the special issue on “Emerging research in Internet of Things” 67
Application Specific Routing Algorithms for Low Power Network on Chip Design 66
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 66
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 65
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 65
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 63
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 63
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 63
Tuning methodologies for parameterized systems design 63
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 62
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 62
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 62
Data Encoding Schemes in Networks on Chip 62
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 61
NoC Links Energy Reduction through Link Voltage Scaling 60
Many-core System-on-Chip: architectures and applications 60
An Instruction-Level Power Analysis Model with Data Dependency 60
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 59
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 59
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 59
Noxim: An open, extensible and cycle-accurate network on chip simulator 59
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 58
Introduction to the special issue on NoC-based many-core architectures 58
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 57
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 56
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 56
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 56
Editorial of the Special issue on Many-core Embedded Systems 56
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 55
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 55
Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support 55
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 55
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems 55
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 54
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 54
An Offline Method for Designing Adaptive Routing Based on Pressure Model 54
Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions 54
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems 53
Special issue on emerging on-chip networks and architectures [Editorial] 53
Introduction to the Special Issue on Network-on-Chip Architectures 53
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 52
Totale 7.727
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Categoria #
all - tutte 61.188
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 61.188
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020181 0 0 0 0 0 0 0 0 0 27 153 1
2020/20211.034 126 0 124 124 6 127 1 179 1 139 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.074 46 63 147 19 177 141 107 161 202 11 0 0
Totale 8.962