IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 5.891
EU - Europa 4.168
AS - Asia 1.840
SA - Sud America 403
AF - Africa 26
Continente sconosciuto - Info sul continente non disponibili 18
Totale 12.346
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Nazione #
US - Stati Uniti d'America 5.638
IE - Irlanda 1.480
SG - Singapore 934
UA - Ucraina 786
FR - Francia 627
GB - Regno Unito 469
BR - Brasile 347
HK - Hong Kong 320
CN - Cina 261
DE - Germania 260
CA - Canada 218
SE - Svezia 165
CH - Svizzera 130
FI - Finlandia 98
IN - India 77
TR - Turchia 55
VN - Vietnam 51
IT - Italia 34
RU - Federazione Russa 28
IR - Iran 23
IQ - Iraq 19
MX - Messico 19
AR - Argentina 17
EU - Europa 17
KR - Corea 17
PL - Polonia 17
JP - Giappone 15
NL - Olanda 12
CZ - Repubblica Ceca 11
ES - Italia 11
PK - Pakistan 10
BD - Bangladesh 9
BE - Belgio 8
EC - Ecuador 8
CL - Cile 7
PE - Perù 7
SA - Arabia Saudita 7
DK - Danimarca 6
IL - Israele 6
MA - Marocco 6
UZ - Uzbekistan 6
ZA - Sudafrica 6
LT - Lituania 5
PY - Paraguay 5
VE - Venezuela 5
AL - Albania 3
AZ - Azerbaigian 3
CO - Colombia 3
HU - Ungheria 3
ID - Indonesia 3
JM - Giamaica 3
NI - Nicaragua 3
PH - Filippine 3
AM - Armenia 2
BN - Brunei Darussalam 2
DZ - Algeria 2
EG - Egitto 2
HN - Honduras 2
JO - Giordania 2
KE - Kenya 2
KG - Kirghizistan 2
NP - Nepal 2
OM - Oman 2
PT - Portogallo 2
RO - Romania 2
RS - Serbia 2
TN - Tunisia 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BJ - Benin 1
BO - Bolivia 1
CR - Costa Rica 1
DO - Repubblica Dominicana 1
EE - Estonia 1
GE - Georgia 1
GR - Grecia 1
GT - Guatemala 1
GY - Guiana 1
IM - Isola di Man 1
IS - Islanda 1
KZ - Kazakistan 1
LB - Libano 1
LK - Sri Lanka 1
LR - Liberia 1
LV - Lettonia 1
MU - Mauritius 1
MY - Malesia 1
NG - Nigeria 1
PR - Porto Rico 1
PS - Palestinian Territory 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
SR - Suriname 1
SV - El Salvador 1
SY - Repubblica araba siriana 1
TH - Thailandia 1
TT - Trinidad e Tobago 1
TW - Taiwan 1
Totale 12.342
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Città #
Dublin 1.476
Chandler 905
Dallas 849
Jacksonville 773
Singapore 473
London 420
San Jose 337
Hong Kong 319
Boardman 274
Ashburn 271
Chicago 207
Toronto 193
The Dalles 163
Beijing 152
Santa Clara 146
Zurich 130
Princeton 124
Wilmington 121
Helsinki 97
Dearborn 59
Frankfurt am Main 41
Istanbul 38
Cedar Knolls 35
São Paulo 29
Des Moines 22
Norwalk 22
Los Angeles 19
Seoul 17
Leawood 16
New York 16
Hanoi 15
Pune 15
Tokyo 15
Edinburgh 14
Cambridge 13
Council Bluffs 13
San Francisco 13
Ho Chi Minh City 12
Kocaeli 12
Rio de Janeiro 12
Augusta 11
Brno 11
Bremen 10
Munich 10
Amsterdam 9
Ardabil 9
Belo Horizonte 9
Kunming 9
San Mateo 9
Brooklyn 8
Brussels 8
Milan 8
Monmouth Junction 8
Ottawa 8
Warsaw 8
Zanjan 8
Atlanta 7
Düsseldorf 7
Las Vegas 7
Manchester 7
Phoenix 7
Wroclaw 7
Copenhagen 6
Fairfield 6
Guangzhou 6
Guarulhos 6
Guwahati 6
Lauterbourg 6
Moscow 6
Nanjing 6
Redmond 6
Tashkent 6
Baghdad 5
Bexley 5
Fresnillo 5
Hefei 5
Hillsboro 5
Karachi 5
Lima 5
Montreal 5
Porto Alegre 5
Ann Arbor 4
Belém 4
Campinas 4
Chennai 4
Cotia 4
Falkenstein 4
Franca 4
Glasgow 4
Jeddah 4
Mexico City 4
Newark 4
Osasco 4
Saint Petersburg 4
Tel Aviv 4
Andover 3
Asunción 3
Baku 3
Bangalore 3
Brasília 3
Totale 8.239
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Nome #
A genetic bus encoding technique for power optimization of embedded systems 189
A genetic approach to bus encoding 182
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 180
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 178
A Communication-Aware Topological Mapping Technique for NoCs 177
A Framework for Design Space Exploration of Parameterized VLSI Systems 172
Special Section on ESTIMedia’13 165
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 161
Introduction to the special section on on-chip and off-chip network architectures 155
Exploiting Data Resilience in Wireless Network-on-chip Architectures 155
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 153
Editorial 151
Introduction to the special section on ESTIMedia'12 147
Cycle-Accurate Network on Chip Simulation with Noxim 146
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 139
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 139
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 136
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 132
A new selection policy for adaptive routing in network on chip 126
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 122
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 121
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 116
Multi-Objective Optimization of a Parameterized VLIW Architecture 115
An evolutionary approach for reducing the switching activity in address buses 114
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 114
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 112
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 112
Bandwidth Aware Routing Algorithms for Networks-on-Chip 111
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 111
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 111
Improving Wormhole Adaptive Routing in Networks on Chip 109
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 108
Network-on-chip architectures and design methodologies 108
Tuning methodologies for parameterized systems design 108
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 108
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 107
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 107
An Evolutionary Approach to Network on Chip Mapping Problem 106
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 105
An evolutionary Approach for reducing the energy in address buses 105
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 105
Power-Aware Selection Policy for Networks on Chip 104
A Novel Approach to Design Space Exploration of Parameterized SOCs 104
Networks-on-Chip: Emerging Research Topics and Novel Ideas 102
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 101
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 101
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 100
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 100
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 99
High Performance Computing for Embedded System Design: A Case Study 99
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 98
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 97
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 96
Parameterised System Design Based on Genetic Algorithms 95
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 95
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 94
Design Space Exploration Methodologies for IP-based System-on-a-chip 94
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 94
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 94
Multi-objective mapping for mesh-based NoC architectures 93
An evolutionary approach for Pareto-optimal configurations in SOC platforms 93
Exploring Design Space of VLIW Architectures 91
Multi-objective design space exploration using genetic algorithms 91
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 91
Fuzzy Decision Making in Embedded System Design 90
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 89
Application Specific Routing Algorithms for Low Power Network on Chip Design 89
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints 89
Many-core System-on-Chip: architectures and applications 89
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 88
Noxim: An open, extensible and cycle-accurate network on chip simulator 87
Introduction to the special issue on “Emerging research in Internet of Things” 87
An Instruction-Level Power Analysis Model with Data Dependency 87
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 86
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 85
A Closed Loop Control based Power Manager for WiNoC Architectures 85
Message from the Chairs 84
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 84
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 84
Data Encoding Schemes in Networks on Chip 84
Power/Energy Perspective on Hyperblock Formation 83
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 83
NoC Links Energy Reduction through Link Voltage Scaling 83
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 82
Editorial of the Special issue on Many-core Embedded Systems 82
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 82
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 81
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 81
Guest Editors’ Introduction to the Special Issue on Novel On-Chip Parallel Architectures and Software Support 81
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 81
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 81
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 80
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 80
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip 80
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 80
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip 79
Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms 78
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 78
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems 78
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 78
Totale 10.642
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Categoria #
all - tutte 75.652
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 75.652
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021207 0 0 0 0 0 0 0 0 0 0 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.637 46 63 147 19 177 141 107 161 202 216 246 112
2025/20262.895 240 777 265 144 116 191 321 303 297 199 42 0
Totale 12.420