IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 4.162
EU - Europa 4.074
AS - Asia 1.159
SA - Sud America 329
Continente sconosciuto - Info sul continente non disponibili 18
AF - Africa 15
Totale 9.757
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Nazione #
US - Stati Uniti d'America 3.926
IE - Irlanda 1.479
UA - Ucraina 782
FR - Francia 607
GB - Regno Unito 462
SG - Singapore 448
BR - Brasile 297
HK - Hong Kong 297
DE - Germania 234
CA - Canada 214
CN - Cina 193
SE - Svezia 165
CH - Svizzera 130
FI - Finlandia 98
IN - India 66
TR - Turchia 52
IR - Iran 23
IT - Italia 21
RU - Federazione Russa 20
EU - Europa 17
KR - Corea 17
MX - Messico 14
PL - Polonia 12
CZ - Repubblica Ceca 11
IQ - Iraq 10
NL - Olanda 9
BE - Belgio 8
ES - Italia 8
VN - Vietnam 8
AR - Argentina 7
DK - Danimarca 6
EC - Ecuador 6
JP - Giappone 6
PE - Perù 6
ZA - Sudafrica 6
BD - Bangladesh 5
IL - Israele 5
PY - Paraguay 5
UZ - Uzbekistan 5
PK - Pakistan 4
AL - Albania 3
CL - Cile 3
HU - Ungheria 3
LT - Lituania 3
MA - Marocco 3
SA - Arabia Saudita 3
AM - Armenia 2
AZ - Azerbaigian 2
BN - Brunei Darussalam 2
HN - Honduras 2
KG - Kirghizistan 2
OM - Oman 2
RO - Romania 2
TN - Tunisia 2
VE - Venezuela 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BO - Bolivia 1
DZ - Algeria 1
EE - Estonia 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
GT - Guatemala 1
GY - Guiana 1
ID - Indonesia 1
IM - Isola di Man 1
IS - Islanda 1
JM - Giamaica 1
JO - Giordania 1
KZ - Kazakistan 1
LB - Libano 1
LV - Lettonia 1
NG - Nigeria 1
NI - Nicaragua 1
NP - Nepal 1
PR - Porto Rico 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TT - Trinidad e Tobago 1
UY - Uruguay 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 9.757
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Città #
Dublin 1.475
Chandler 905
Jacksonville 773
London 418
Hong Kong 297
Boardman 274
Singapore 199
Toronto 193
Beijing 142
Santa Clara 133
Zurich 130
Princeton 124
Wilmington 121
Helsinki 97
Ashburn 96
The Dalles 92
Chicago 73
Dearborn 59
Dallas 56
Istanbul 37
Cedar Knolls 35
São Paulo 27
Norwalk 22
Los Angeles 19
Des Moines 17
Frankfurt am Main 17
Seoul 17
Leawood 16
Pune 15
Edinburgh 14
Cambridge 13
San Francisco 13
Kocaeli 12
Augusta 11
Brno 11
New York 11
Bremen 10
Munich 10
Ardabil 9
Kunming 9
San Mateo 9
Belo Horizonte 8
Brussels 8
Milan 8
Monmouth Junction 8
Ottawa 8
Rio de Janeiro 8
Zanjan 8
Atlanta 7
Brooklyn 7
Düsseldorf 7
Las Vegas 7
Phoenix 7
Warsaw 7
Amsterdam 6
Copenhagen 6
Fairfield 6
Guwahati 6
Lauterbourg 6
Manchester 6
Nanjing 6
Redmond 6
Tokyo 6
Fresnillo 5
Guangzhou 5
Guarulhos 5
Hefei 5
Montreal 5
Tashkent 5
Ann Arbor 4
Belém 4
Campinas 4
Chennai 4
Cotia 4
Falkenstein 4
Franca 4
Lima 4
Newark 4
Saint Petersburg 4
Andover 3
Asunción 3
Bangalore 3
Bexley 3
Budapest 3
Curitiba 3
Dalsjoefors 3
Glasgow 3
Hanoi 3
Juiz de Fora 3
Moscow 3
Nanchang 3
Niterói 3
Osasco 3
Porto Alegre 3
Sacramento 3
Seattle 3
São Bernardo do Campo 3
São José dos Campos 3
Tel Aviv 3
Wroclaw 3
Totale 6.296
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Nome #
A genetic bus encoding technique for power optimization of embedded systems 152
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 152
A genetic approach to bus encoding 149
A Framework for Design Space Exploration of Parameterized VLSI Systems 148
A Communication-Aware Topological Mapping Technique for NoCs 143
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 142
Special Section on ESTIMedia’13 142
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 136
Introduction to the special section on on-chip and off-chip network architectures 135
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 133
Exploiting Data Resilience in Wireless Network-on-chip Architectures 133
Introduction to the special section on ESTIMedia'12 131
Editorial 131
Cycle-Accurate Network on Chip Simulation with Noxim 124
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 120
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 106
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 104
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 104
A new selection policy for adaptive routing in network on chip 102
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 97
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 96
Bandwidth Aware Routing Algorithms for Networks-on-Chip 93
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 93
Improving Wormhole Adaptive Routing in Networks on Chip 92
Multi-Objective Optimization of a Parameterized VLIW Architecture 91
An evolutionary approach for reducing the switching activity in address buses 90
Power-Aware Selection Policy for Networks on Chip 89
Network-on-chip architectures and design methodologies 87
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 87
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 86
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 86
Networks-on-Chip: Emerging Research Topics and Novel Ideas 84
An Evolutionary Approach to Network on Chip Mapping Problem 84
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 83
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 83
Design Space Exploration Methodologies for IP-based System-on-a-chip 82
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 81
Tuning methodologies for parameterized systems design 81
A Novel Approach to Design Space Exploration of Parameterized SOCs 81
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 81
Parameterised System Design Based on Genetic Algorithms 80
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 80
Multi-objective design space exploration using genetic algorithms 79
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 79
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 79
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 78
An evolutionary Approach for reducing the energy in address buses 78
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 78
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 78
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 77
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 77
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 77
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 76
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 75
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 75
High Performance Computing for Embedded System Design: A Case Study 75
Message from the Chairs 74
Fuzzy Decision Making in Embedded System Design 74
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 74
An evolutionary approach for Pareto-optimal configurations in SOC platforms 73
Exploring Design Space of VLIW Architectures 72
Application Specific Routing Algorithms for Low Power Network on Chip Design 72
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 72
Multi-objective mapping for mesh-based NoC architectures 72
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 71
Many-core System-on-Chip: architectures and applications 71
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 70
Introduction to the special issue on “Emerging research in Internet of Things” 70
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 69
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 69
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 69
Tuning methodologies for parameterized systems design 69
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 69
Data Encoding Schemes in Networks on Chip 69
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 68
Noxim: An open, extensible and cycle-accurate network on chip simulator 67
An Instruction-Level Power Analysis Model with Data Dependency 67
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 66
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 66
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 65
NoC Links Energy Reduction through Link Voltage Scaling 64
Introduction to the special issue on NoC-based many-core architectures 64
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 63
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems 63
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 62
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 62
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 62
Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions 62
A Closed Loop Control based Power Manager for WiNoC Architectures 62
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 62
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 61
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 61
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 61
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 61
Editorial of the Special issue on Many-core Embedded Systems 61
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 61
An Offline Method for Designing Adaptive Routing Based on Pressure Model 61
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 60
Special issue on emerging on-chip networks and architectures [Editorial] 60
Introduction to the Special Issue on Network-on-Chip Architectures 60
Totale 8.466
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Categoria #
all - tutte 67.794
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 67.794
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021908 0 0 124 124 6 127 1 179 1 139 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.637 46 63 147 19 177 141 107 161 202 216 246 112
2025/2026306 240 66 0 0 0 0 0 0 0 0 0 0
Totale 9.831