IRIS
PALESI, MAURIZIO
 Distribuzione geografica
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Continente #
EU - Europa 4.049
NA - Nord America 4.031
AS - Asia 1.074
SA - Sud America 269
Continente sconosciuto - Info sul continente non disponibili 18
AF - Africa 8
Totale 9.449
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Nazione #
US - Stati Uniti d'America 3.804
IE - Irlanda 1.479
UA - Ucraina 781
FR - Francia 604
GB - Regno Unito 456
SG - Singapore 415
HK - Hong Kong 285
BR - Brasile 249
DE - Germania 230
CA - Canada 211
CN - Cina 193
SE - Svezia 163
CH - Svizzera 130
FI - Finlandia 98
IN - India 52
TR - Turchia 51
IR - Iran 23
IT - Italia 21
RU - Federazione Russa 19
EU - Europa 17
KR - Corea 17
CZ - Repubblica Ceca 11
MX - Messico 11
PL - Polonia 9
BE - Belgio 8
NL - Olanda 8
AR - Argentina 6
DK - Danimarca 6
ES - Italia 5
IL - Israele 5
UZ - Uzbekistan 5
EC - Ecuador 4
JP - Giappone 4
AL - Albania 3
HU - Ungheria 3
MA - Marocco 3
PE - Perù 3
PK - Pakistan 3
AM - Armenia 2
AZ - Azerbaigian 2
BD - Bangladesh 2
BN - Brunei Darussalam 2
IQ - Iraq 2
KG - Kirghizistan 2
LT - Lituania 2
PY - Paraguay 2
RO - Romania 2
ZA - Sudafrica 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BB - Barbados 1
BG - Bulgaria 1
BO - Bolivia 1
CL - Cile 1
EE - Estonia 1
EG - Egitto 1
GE - Georgia 1
GR - Grecia 1
GT - Guatemala 1
GY - Guiana 1
HN - Honduras 1
ID - Indonesia 1
IM - Isola di Man 1
IS - Islanda 1
JO - Giordania 1
KZ - Kazakistan 1
LV - Lettonia 1
NP - Nepal 1
OM - Oman 1
PR - Porto Rico 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SA - Arabia Saudita 1
SI - Slovenia 1
SK - Slovacchia (Repubblica Slovacca) 1
TN - Tunisia 1
TT - Trinidad e Tobago 1
UY - Uruguay 1
VE - Venezuela 1
VN - Vietnam 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 9.449
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Città #
Dublin 1.475
Chandler 905
Jacksonville 773
London 417
Hong Kong 285
Boardman 274
Toronto 193
Singapore 190
Beijing 142
Santa Clara 130
Zurich 130
Princeton 124
Wilmington 120
Helsinki 97
The Dalles 92
Ashburn 87
Chicago 68
Dearborn 59
Istanbul 37
Cedar Knolls 35
Norwalk 22
São Paulo 21
Des Moines 17
Los Angeles 17
Seoul 17
Frankfurt am Main 16
Leawood 16
Pune 15
Edinburgh 14
Cambridge 13
San Francisco 13
Kocaeli 12
Augusta 11
Brno 11
Bremen 10
Ardabil 9
Kunming 9
San Mateo 9
Belo Horizonte 8
Brussels 8
Milan 8
Monmouth Junction 8
Zanjan 8
Düsseldorf 7
Munich 7
Ottawa 7
Amsterdam 6
Atlanta 6
Brooklyn 6
Copenhagen 6
Fairfield 6
Las Vegas 6
Lauterbourg 6
Nanjing 6
Redmond 6
Fresnillo 5
Guangzhou 5
Hefei 5
New York 5
Phoenix 5
Rio de Janeiro 5
Tashkent 5
Warsaw 5
Ann Arbor 4
Belém 4
Falkenstein 4
Franca 4
Guarulhos 4
Montreal 4
Saint Petersburg 4
Tokyo 4
Andover 3
Bangalore 3
Budapest 3
Campinas 3
Chennai 3
Curitiba 3
Dalsjoefors 3
Glasgow 3
Juiz de Fora 3
Manchester 3
Moscow 3
Nanchang 3
Newark 3
Osasco 3
Porto Alegre 3
Sacramento 3
Seattle 3
São Bernardo do Campo 3
Tel Aviv 3
Aci Catena 2
Assis 2
Asunción 2
Azor 2
Baku 2
Bandar Seri Begawan 2
Bexley 2
Bishkek 2
Borås 2
Boston 2
Totale 6.149
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Nome #
A genetic bus encoding technique for power optimization of embedded systems 147
A genetic approach to bus encoding 146
A Framework for Design Space Exploration of Parameterized VLSI Systems 145
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 145
Special Section on ESTIMedia’13 141
A Communication-Aware Topological Mapping Technique for NoCs 139
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 137
Introduction to the special section on on-chip and off-chip network architectures 135
On Self-tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 134
Reducing Complexity of Multi-objective Design Space Exploration in VLIW-based Embedded Systems 133
Editorial 130
Introduction to the special section on ESTIMedia'12 129
Exploiting Data Resilience in Wireless Network-on-chip Architectures 124
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks 118
Cycle-Accurate Network on Chip Simulation with Noxim 118
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 102
Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms 101
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures 100
A new selection policy for adaptive routing in network on chip 99
Multiobjective Genetic Approach for System-Level Exploration in Parameterized Systems-on-a-Chip 95
A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms 95
Bandwidth Aware Routing Algorithms for Networks-on-Chip 91
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 91
An evolutionary approach for reducing the switching activity in address buses 89
Power-Aware Selection Policy for Networks on Chip 88
Improving Wormhole Adaptive Routing in Networks on Chip 88
Run-time Deadlock Detection in Networks-on-Chip using Coupled Transitive Closure Networks 85
Multi-Objective Optimization of a Parameterized VLIW Architecture 85
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 85
Network-on-chip architectures and design methodologies 84
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design 83
An Evolutionary Approach to Network on Chip Mapping Problem 81
Networks-on-Chip: Emerging Research Topics and Novel Ideas 80
Design Space Exploration Methodologies for IP-based System-on-a-chip 80
A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems 80
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 80
A Novel Approach to Design Space Exploration of Parameterized SOCs 80
Parameterised System Design Based on Genetic Algorithms 79
Tuning methodologies for parameterized systems design 79
Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-objective Scenario 78
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs 78
An evolutionary Approach for reducing the energy in address buses 77
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded architectures 76
Adaptive Power Allocation for Many-core Systems Inspired from A Multi-agent Auction Model 76
Multi-objective design space exploration using genetic algorithms 75
Low Latency and Energy Efficient Multicasting Schemes for 3D NoC-based SoCs 74
Hyperblock formation: a power/energy perspective for high performance VLIW architectures 74
Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms 74
A Multi-objective Strategy for Concurrent Mapping and Routing in Networks on Chip 74
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 74
An hybrid approach for automatic gait events detection using a triaxial accelerometer sensor 74
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 73
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks on Chip 73
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 73
Fuzzy Decision Making in Embedded System Design 73
High Performance Computing for Embedded System Design: A Case Study 73
Message from the Chairs 72
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 72
Application Specific Routing Algorithms for Low Power Network on Chip Design 71
Multi-objective mapping for mesh-based NoC architectures 71
An evolutionary approach for Pareto-optimal configurations in SOC platforms 71
Exploring Design Space of VLIW Architectures 70
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 70
An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip 69
Introduction to the special issue on “Emerging research in Internet of Things” 69
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 68
An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures 68
Improving the Teaching Effectiveness in an Introductory Computer Architecture Course 67
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 67
Many-core System-on-Chip: architectures and applications 67
Tuning methodologies for parameterized systems design 66
Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems 66
Editorial on Special issue on energy efficient methods and systems in the emerging cloud era 66
Data Encoding Schemes in Networks on Chip 66
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions 65
Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC 65
An Instruction-Level Power Analysis Model with Data Dependency 65
NoC Links Energy Reduction through Link Voltage Scaling 64
Efficient Congestion-Aware Scheme for Wireless on-Chip Networks 64
Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator 63
Embedded Transitive-Closure Network for Run-Time Deadlock Detection in Networks-on-Chip 62
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 62
Noxim: An open, extensible and cycle-accurate network on chip simulator 62
Introduction to the special issue on NoC-based many-core architectures 62
HiRA: A Methodology for Deadlock Free Routing in Hierarchical Networks on Chip 61
Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip 61
Performance Evaluation of Efficient Multi-Objective Evolutionary Algorithms for Design Space Exploration of Embedded Computer Systems 61
On Self-Tuning Networks-on-Chip for Dynamic Network-Flow Dominance Adaptation 61
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems 60
A Closed Loop Control based Power Manager for WiNoC Architectures 60
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 60
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links 58
Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip 58
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems 58
Editorial of the Special issue on Many-core Embedded Systems 58
An Offline Method for Designing Adaptive Routing Based on Pressure Model 58
Deadlock free Routing Algorithms for Irregular Mesh Topology NoC Systems with Rectangular Regions 58
Power-Efficient, High Performance General Purpose and Application Specific Computing Architectures 57
Run-Time Deadlock Detection. In Routing Algorithms in Networks-on-Chip 57
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 57
Totale 8.203
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Categoria #
all - tutte 64.815
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 64.815
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201 0 0 0 0 0 0 0 0 0 0 0 1
2020/20211.034 126 0 124 124 6 127 1 179 1 139 67 140
2021/2022814 3 11 8 267 0 1 11 119 40 89 48 217
2022/20232.857 288 301 167 439 327 344 74 266 327 64 206 54
2023/20241.528 91 192 110 81 242 64 409 90 32 39 40 138
2024/20251.635 46 63 147 19 177 141 107 161 202 216 246 110
Totale 9.523